This invention relates to static random access memories and in particular to a bit-line load for use in such memories.
The conventional diode bit-line load commonly used in static random access memories suffers from two serious disadvantages. The first of these is the so called V.sub.dd bump problem whereby a fall in the V.sub.dd voltage e.g. from V.sub.1 to V.sub.2 traps the bit-line at a voltage equal to V.sub.1 -V.sub.T1 (where V.sub.T1 is the diode threshold voltage) rather than the desired voltage V.sub.2 -V.sub.T1. On a subsequent access the memory cell must then discharge the bit-line by an additional voltage equal to V.sub.1 -V.sub.2 resulting in a slow access on this particular cycle.
The second problem with conventional diode loads in the relatively high V.sub.dd current associated with the write cycle. For example, in a conventional memory, the current flowing through a bit-line can be increased by two orders of magnitude over the current flowing during a read cycle. This problem is of course accentuated with wide memories where many bit-lines may be written to causing a large current drain, for example byte wide memories where eight bit-lines will be written to simultaneously.
The object of the present invention is to minimise or to overcome these disadvantages.